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50英寸LED背光液晶电视屏结构与电气接口技术规范

2012-08-30 09:13:05  编辑:航行 来源:数字音视工程网
2012-08-29 中国电子视像行业协会发布《50英寸LED背光液晶电视屏结构与电气接口技术规范》的中国电子视像行业协会标准CVIA-TJ-LCD/LED-2012-08

  中国电子视像行业协会标准

  CVIA-TJ-LCD/LED-2012-08

  50英寸LED背光液晶电视屏结构与电气接口技术规范

  (2.0版本)修订稿

2012-x-x发布
2012-x-x实施
发 布

中国电子视像行业协会

  目 录

  前言………………………………………………………………………………………………………1

  1、范围………………………………………………………………………………………………… 2

  2、结构部分…………………………………………………………………………………………… 2

  3、电气接口部分……………………………………………………………………………………… 6

  前 言

  本规范是中国电子视像行业协会的推荐性标准,是协会相关会员单位在组织技术研发、采购和生产过程中的主要参照标准,也推荐其它相关企业参考采用。

  LED背光液晶电视屏结构与电气接口技术规范,是根据产业和市场的发展需求,由中国电子视像行业协会(简称“视像协会”)组织相关会员单位,共同制定的推荐性标准。本规范旨在为企业提供彩色电视机用液晶显示屏在结构和电气接口参数方面的一致性,以达到降低生产成本、规范生产秩序、促进市场繁荣的目的。

  本规范主要起草单位(排名不分先后):青岛海信电器股份有限公司、厦门华侨电子股份有限公司、TCL集团股份有限公司、青岛海尔电子有限公司、深圳创维-RGB电子有限公司、四川长虹电器股份有限公司、康佳集团股份有限公司、南京熊猫电子集团有限公司。

  本规范V2.0版主要是在V1.0版基础上增加了对于更窄边框屏和3D屏的相关定义。

  本规范的所有权、解释权和修订权属于中国电子视像行业协会。

  1、范围

  本标准给出了50英寸LED背光液晶电视屏(以下简称为“屏”)的结构和电气接口技术规范,这些规范是根据目前中国市场上被共同认可的主流产品规范而确定。

  2、结构部分[1]

  2.1 关于外形长宽尺寸为1122.64 mm×645.31 mm、两侧边框宽度为9.9mm的屏

  2.1.1 屏正面与背面的结构布局示意图分别见图1和图2,结构尺寸图分别见图3和图4(详细数据见附件4和附件6的2D图纸)。

  2.1.2 屏的外形结构尺寸:

  2.1.2.1 外形长宽尺寸为1122.64 mm×645.31 mm。

  2.1.2.2 边框宽度:上、 侧边框为9.9mm,下边框为12mm。

  2.1.2.3 侧边和顶部边框厚度≤15.1mm,底部边框厚度≤18.4mm。

  2.1.2.4 屏边框正面到屏玻璃的距离:1.2mm-18mm。

  2.1.3 屏背部基本参数:

  2.1.3.1 壁挂采用400×400的标准(为内嵌式盲孔螺柱),壁挂螺柱端面到屏边框正面的高度

  为21.8mm,内螺纹M6,螺柱外径为φ14mm。

  2.1.3.2 底座的立柱固定位置:凸包到屏边框正面的高度为16.4mm,螺孔为M4。屏厂家在开

  发新屏时,如需更改,应第一时间通知视像协会并与起草本规范的整机厂沟通,提供合

  适的立柱固定位置。

  2.1.3.3 固定主板和电源板的螺孔为M3,凸包小端直径为φ8,大端直径≤φ20;其它位置的

  M4凸包小端直径为φ12。

  2.1.3.4 固定主板的凸包高度:凸包顶面到屏边框正面的高度为15.8mm。

  2.1.3.5 固定电源板的凸包高度:凸包顶面到屏边框正面的高度为18.3mm。

  2.1.3.6 固定音箱的凸包高度:凸包顶面到屏边框正面的高度为15.8mm。

  2.1.3.7 凸包和螺柱安装孔深度规格:标称深度≧4.8mm,特殊孔规格单独标出。

  2.1.4 屏背面螺孔位置如图4,标称深度≥4.0mm。

  2.1.5 屏顶侧和两侧卡扣方孔(尺寸为12×3) 的位置如图3,方孔的深度≧2.0mm。

  2.1.6 LED Driver板(即Converter板),位置在图2左上角,屏厂家可根据Driver板的大小排布,

  但不能干涉到Driver板下面的凸包。

  2.1.7 屏的详细结构尺寸见附件3的3D图纸。

  图1 50英寸LED背光液晶电视屏正面结构布局示意图(9.9mm侧边框)

  图2 50英寸LED背光液晶电视屏背面结构布局示意图(9.9mm侧边框)

  图3 50英寸LED背光液晶电视屏正面结构布局示意图尺寸图(9.9mm侧边框)

  图4 50英寸LED背光液晶电视屏背面结构布局示意图尺寸图(9.9mm侧边框)

  3、电气接口部分

  3.1 LED Driver接口定义如下:

PIN Symbol Description
1 VDDB Operating Voltage Supply, +24V DC regulated
2 VDDB Operating Voltage Supply, +24V DC regulated
3 VDDB Operating Voltage Supply, +24V DC regulated
4 VDDB Operating Voltage Supply, +24V DC regulated
5 VDDB Operating Voltage Supply, +24V DC regulated
6 BLGND Ground and Current Return
7 BLGND Ground and Current Return
8 BLGND Ground and Current Return
9 BLGND Ground and Current Return
10 BLGND Ground and Current Return
11 DET BLU status detection: Normal : 0~0.8V ; Abnormal : Open collector
12 VBLON BLU On-Off control: High /Open(3.3V) : BL On ; Low (-0.3~0.8V/GND) : BL Off
13 VDIM N.C for no DC dimming. Or Internal PWM (0~3.3V for 20~100% Duty, open for 100%) < NC ; at External PWM mode>
14 PDIM External PWM (10%~100% Duty, open for 100%) < NC ;at Internal PWM mode>

  3.2 LVDS接口定义如下:

  3.2.1 51-pin的定义(适用于60HZ/120HZ 2D/3D SG/PR屏):

PIN Name Description
1 N.C. No connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 L/R out(SG) High(3.3V) : L;
Low(GND) : R
or:N.C. No Connection
6 ROTATE High(3.3V) : Rotate enable(Data mirror); Open/Low(GND) : Normal
or:N.C. No Connection
7 SELLVDS Open/High(3.3V) for NS, Low(GND) for JEIDA
8 DCR1 DCR PWM Dimming Signal Input
Duty: TBD%~100% (0~3.3V)
or:N.C. No Connection
9 DCR2 DCR PWM Dimming Signal Output
Duty: TBD%~100% (0~3.3V)
or:N.C. No Connection
10 DCR3 DCR Function ON/OFF Selection
Low(GND)/Open : DCR Function Disable(Bypass DIM_IN)
High(3.3V) : DCR Function Enable
or:N.C. No Connection
or:2D/3D PR) High(3.3V) : PR 3D
Low(GND)/ Open : 2D
11 GND Ground
12 CH1[0]- First pixel Negative LVDS differential data input. Pair 0
13 CH1[0]+ First pixel Positive LVDS differential data input. Pair 0
14 CH1[1]- First pixel Negative LVDS differential data input. Pair 1
15 CH1[1]+ First pixel Positive LVDS differential data input. Pair 1
16 CH1[2]- First pixel Negative LVDS differential data input. Pair 2
17 CH1[2]+ First pixel Positive LVDS differential data input. Pair 2
18 GND Ground
19 CH1CLK- First pixel Negative LVDS differential clock input.
20 CH1CLK+ First pixel Positive LVDS differential clock input.
21 GND Ground
22 CH1[3]- First pixel Negative LVDS differential data input. Pair 3
23 CH1[3]+ First pixel Positive LVDS differential data input. Pair 3
24 CH1[4]- /NC First pixel Negative LVDS differential data input. Pair 4(10bit) /NC(8bit)
25 CH1[4]+ /NC First pixel Positive LVDS differential data input. Pair 4(10bit) /NC(8bit)
26 2D/3D(SG) Input signal for 2D/3D Mode Selection 2.7~3.3V:SG 3D;0~0.7V:2D
or:N.C. No Connection
27 L/R in Input signal for Left Right eye frame synchronous 2.7~3.3V:L;0~0.7V:R
or:N.C. No Connection
28 CH2[0]- Second pixel Negative LVDS differential data input. Pair 0
29 CH2[0]+ Second pixel Positive LVDS differential data input. Pair 0
30 CH2[1]- Second pixel Negative LVDS differential data input. Pair 1
31 CH2[1]+ Second pixel Positive LVDS differential data input. Pair 1
32 CH2[2]- Second pixel Negative LVDS differential data input. Pair 2
33 CH2[2]+ Second pixel Positive LVDS differential data input. Pair 2
34 GND Ground
35 CH2CLK- Second pixel Negative LVDS differential clock input.
36 CH2CLK+ Second pixel Positive LVDS differential clock input.
37 GND Ground
38 CH2[3]- Second pixel Negative LVDS differential data input. Pair 3
39 CH2[3]+ Second pixel Positive LVDS differential data input. Pair 3
40 CH2[4]- /NC Second pixel Negative LVDS differential data input. Pair 4(10bit) /NC(8bit)
41 CH2[4]+ /NC Second pixel Positive LVDS differential data input. Pair 4(10bit) /NC(8bit)
42 N.C. No Connection
or:LD_EN Input signal for Local Diming Enable H(3.3V) /Open: Enable;Low(GND):Disable
43 N.C. No Connection
or:SCN (SG) SCN_EN
L(GND)or Open: Scanning Disable
H(3.3V): Scanning Enable
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
 
3.2.241-pin的定义(适用于120HZ屏):
PIN Symbol Description
1 N.C. No connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 Reserved Internal Use Only (NC)
8 N.C. No Connection
9 GND Ground
10 CH3[0]- Third pixel Negative LVDS differential data input. Pair 0
11 CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0
12 CH3[1]- Third pixel Negative LVDS differential data input. Pair 1
13 CH3[1]+ Third pixel Positive LVDS differential data input. Pair 1
14 CH3[2]- Third pixel Negative LVDS differential data input. Pair 2
15 CH3[2]+ Third pixel Positive LVDS differential data input. Pair 2
16 GND Ground
17 CH3CLK- Third pixel Negative LVDS differential clock input.
18 CH3CLK+ Third pixel Positive LVDS differential clock input.
19 GND Ground
20 CH3[3]- Third pixel Negative LVDS differential data input. Pair 3
21 CH3[3]+ Third pixel Positive LVDS differential data input. Pair 3
22 CH3[4]- /NC Third pixel Negative LVDS differential data input. Pair 4(10bit) /NC(8bit)
23 CH3[4]+ /NC Third pixel Positive LVDS differential data input. Pair 4(10bit) /NC(8bit)
24 GND Ground
25 GND Ground
26 CH4[0]- Fourth pixel Negative LVDS differential data input. Pair 0
27 CH4[0]+ Fourth pixel Positive LVDS differential data input. Pair 0
28 CH4[1]- Fourth pixel Negative LVDS differential data input. Pair 1
29 CH4[1]+ Fourth pixel Positive LVDS differential data input. Pair 1
30 CH4[2]- Fourth pixel Negative LVDS differential data input. Pair 2
31 CH4[2]+ Fourth pixel Positive LVDS differential data input. Pair 2
32 GND Ground
33 CH4CLK- Fourth pixel Negative LVDS differential clock input.
34 CH4CLK+ Fourth pixel Positive LVDS differential clock input.
35 GND Ground
36 CH4[3]- Fourth pixel Negative LVDS differential data input. Pair 3
37 CH4[3]+ Fourth pixel Positive LVDS differential data input. Pair 3
38 CH4[4]- /NC Fourth pixel Negative LVDS differential data input. Pair 4(10bit) /NC(8bit)
39 CH4[4]+ /NC Fourth pixel Positive LVDS differential data input. Pair 4(10bit) /NC(8bit)
40 GND Ground
41 GND Ground

  备注:120Hz按照First、Second、Third、Fourth对应奇、偶、奇、偶像素顺序;

  60Hz按照First、Second对应奇、偶像素顺序。

  3.3 电源和信号时序定义(屏时序包含下列参数信息)

  3.31 LCD驱动电路时序(LCD Driving Circuit)定义如图7

  图7 50英寸LED背光液晶电视屏LCD驱动电路时序

  3.3.2 LED背光驱动时序(Sequence for LED Driver)定义如图8

  图8 50英寸LED背光液晶电视屏LED背光驱动时序

  3.4 屏的SPEC中须对LED Driver接口以及LVDS接口中的全部控制端口进行功能简述、阻抗特性、 端口电压(或者波形)特性等进行明确定义,并同时提供端口电路简图(示例如下表)。

Symbol 功能简述 阻抗特性 I/O Type 端口电压特性 端口电路简图
SCL EEPROM Serial Clock (for local dimming demo function) Open Drain Resistor to GND ≥100Kohm I/O 0V~3.3V
SDA EEPROM Serial Data (for local dimming demo function) Open Drain Resistor to GND ≥100Kohm I/O 0V~3.3V
L/R_O Output signal for Left Right Glasses control ≤1.1Kohm O 0V~0.7V →Right signal, 2.7V~ 3.3V →Left signal
SELLVDS Input signal for LVDS Data Format Selection Resistor to GND ≥100Kohm I 0V~0.7V→JEDIA, 2.7V~3.3V/OPEN→ VESA
2D/3D Input signal for 2D/3D Mode Selection Resistor to GND ≥15Kohm I 0V~0.7V →2D mode, 2.7V ~ 3.3V →3D mode
L/R Input signal for Left Right eye frame synchronous Resistor to GND ≥15Kohm I 0V~0.7V →Right signal, 2.7V~3.3V →Left signal
LD_EN Input signal for Local Dimming Enable Resistor to GND ≥50Kohm I 0V~0.7V -->Disable, 2.7V~3.3V/Open --> Enable
SCN_EN Input signal for Scanning Enable Resistor to GND ≥50Kohm I 0V~0.7V/Open→Disable, 2.7V ~ 3.3V →Enable
 
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